Implementation of a symmetric split FIR filter on an FPGA
Abstract
Implementation of a symmetric split FIR filter on an FPGA
Incoming article date: 16.12.2021It was necessary to develop a filter design option for implementing it on an FPGA in conditions of limited FPGA resources and processing time. Options for constructing filters and sequential optimization of the structure for implementation on an FPGA were considered. Two models were built using the Matlab environment, where the results of signal processing with filters were compared for the same parameters. Simulations have shown that the filters are unique.
Keywords: DSP, FIR filter, pipeline, FPGA