×

You are using an outdated browser Internet Explorer. It does not support some functions of the site.

Recommend that you install one of the following browsers: Firefox, Opera or Chrome.

Contacts:

+7 961 270-60-01
ivdon3@bk.ru

  • Implementation of a symmetric split FIR filter on an FPGA

    It was necessary to develop a filter design option for implementing it on an FPGA in conditions of limited FPGA resources and processing time. Options for constructing filters and sequential optimization of the structure for implementation on an FPGA were considered. Two models were built using the Matlab environment, where the results of signal processing with filters were compared for the same parameters. Simulations have shown that the filters are unique.

    Keywords: DSP, FIR filter, pipeline, FPGA