The paper presents a method for creating model for combinational circuit implementation in FPGA basis, through its original description. This model represents the equivalent circuit of the FPGA logic elements. The scheme can be used for the calculation of various parameters such as speed, area, power consumption etc. The paper proposes to use this model to assess reliability in relation to the single fault in combinational circuit’s parts or the configuration registers. Furthermore, the resulting equivalent circuit can be modified and re-synthesized in the CAD environment to achieve high levels of resistance to a single event upset. Direct estimation of the masking properties of the logic circuit through its original description is impossible because of substantial change in the structure due to the synthesis process. Evaluation of fault tolerance after place and route is not available due to lack of the necessary tools in modern CAD (Altera Quartus II, Xilinx ISE, Synopsys Synplify). To evaluate the reliability of the project one must create custom FPGA netlist analysis tool and tools for modeling combinational circuits.

Keywords: reliability evaluation, re-synthesis, combinational circuits, FPGA, fault injection.