The paper discusses methods for protecting logical elements of combinational circuits from single failures. Until recently, the problem of creating microelectronic devices resistant to single failures in logic elements was relevant primarily in the military and space industries. In these areas, increased requirements are placed on the fault tolerance of circuits due to the influence of external destabilizing factors. Such factors can be heavy charged particles that affect the operation of logic elements and cause their single failures. Due to the scaling of semiconductor devices, technological standards for the design and manufacture of integrated circuits are changing, and the problem of fault tolerance becomes relevant for devices on the civilian market. The article proposes a technique for resynthesising vulnerable sections of logical combinational circuits. To assess stability, it is proposed to use logical constraints obtained by the resolution method.
Keywords: resynthesis, combinational circuits, reliability, logical correlations, resolution method
In this article, we propose methods for designing fault-tolerant structures for Field Programmable Gate Arrays (FPGAs) by forming an internal structure of macro cells (LUTs), with the possibility of correcting single reversible faults in the circuit’s gates. To improve fault tolerance, the failure tolerance of a typical macro cell was assessed, the most vulnerable areas were identified and the most vulnerable parts of the macrocell were protected by means of triple modular redundancy methods. Depending on the expansion of the protected area, various versions of the built-in redundancy were obtained, and various options for minimizing the built-in redundancy were proposed. Experimental work was carried out to form fault-tolerant ISCAS'85 combinational circuit designs in the basis of fault-tolerant FPGAs.
Keywords: combinational circuit, FPGA, field-programmable gate array, LUT, logic synthesis, increase fault tolerant, computer-aided design (CAD), fault injection, single event transient